The present invention relates to an electrically rewritable nonvolatile semiconductor memory device.
In recent years, as one of the electrically rewritable nonvolatile semiconductor memory devices (EEPROM) of the data, NAND type EEPROM is proposed.
NAND type EEPROM has the following structure. A plurality of memory cell having an N-channel FETMOS structure, wherein a charge storage layer (e.g. a floating gate) and a control gate is layered, are connected in series in the form of which sources and drains of adjacent ones are shared. NAND type EEPROM is constituted by connecting between a source line and a bitline as one unit (NAND cell).
FIG. 1A is a circuit diagram of the NAND cell.
In FIG. 1A, memory cells M1 to M8 is connected in series to each other and constitutes a NAND cell. CG1 to CG8 are control gates, respectively. One end of the NAND cell is connected to a bitline BL through a select transistor S1 and the other end is connected to a source line SL through a select transistor S2. SG1, SG2 are select gates, respectively.
FIG. 1B is the figure showing a distribution of the threshold voltage of the conventional memory cell in NAND type EEPROM.
In FIG. 1B, "0" indicates an erase state and "1" indicates a programmed state, respectively. The threshold voltage of the memory cell of the "0" state is the negative voltage of equal to or less than 0V and the threshold voltage of the memory cell of the "1" state has the positive voltage of equal to or more than 0V. "Vth0" is a threshold voltage after erasing data by irradiating ultraviolet rays (hereinafter, called to as an UV erasure) and is substantially established in the middle of the "0" state and the "1" state.
Hereinafter, an operation of the NAND type EEPROM will be explained.
&lt;Data Programming&gt;
0V ("1" programming) or Vcc of, e.g. 3V ("0" programming) line voltages are applied to the bitline BL according to the programmed data. The select gate SG1 is a power supply voltage Vcc and the select gate SG2 is 0V.
In case of "1" programming, since the select transistor S1 connected to the bitline BL turns "on", 0V are transmitted to the channel of the memory cell to which "1" is programmed. Also, in case of "0" programming, since the select transistor turns "off", the channel voltage of the memory cell which is programmed to "0" becomes "Vcc-Vthsg (Vthsg is the threshold voltage of the select gate)", and becomes floating. When the memory cell which has the more positive threshold voltage Vthcell on the bitline side than the memory cell to which "0" is programmed exists, the voltage of the channel of the memory cell to which "0" is programmed becomes "Vcc-Vthcell". Thereafter, the programming voltage Vpp (=about 20V) which the voltage was boosted is applied to the control gate of the memory cell to which is selected to be programmed, the intermediate voltage Vpass (=about 10V) is applied to the control gate of the other unselected memory cells. As a result, when the programming data is "1", since the voltage of the channel is 0V, a high voltage is applied among the floating gate of the memory cell to which is selected to be programmed and the p-type well or the p-type substrate, then, electrons are tunnel-injected from the p-type well or the p-type substrate to the floating gate. This makes the threshold voltage of the memory cell which is selected to be programmed moving to the positive direction. When the programmed data is "0", the voltage of the floating channel becomes the intermediate voltage by the capacitive coupling with the control gate and the electrons are not injected to the floating gate.
&lt;Data Erasure&gt;
The erasure of the data is substantially performed at the same time by the block unit. That is, the voltage of all control gates in the block which erases data and the voltage of the select gate are set to 0V, respectively, and the boosted voltage VppE (=about 20V) which is boosted is applied to each of the p-type wells and the n-type substrate. Then, the boosted voltage VppE is applied respectively to the control gate and the select gate in the block which does not erase data. Thereby, at the memory cells in the block which erases data, the electrons in the floating gate is discharged by the p-type well and each threshold voltage moves to the negative direction.
&lt;Data Read&gt;.
A data reading is performed as follows. The bitline BL is set at a floating state after being precharged. Then, the voltage of the control gate of the memory cell which is selected to be read is set at the reading voltage of 0V, the voltage of the control gate of the other memory cells and the voltage of the select gate are set at a unselected read voltage Vread (power supply voltage Vcc), respectively, and a source line is set at 0V. Then, whether or not the current flows through the memory cell which is selected to be read is detected by the bitline BL. That is, since the memory cell becomes "off" state if the programmed data in the memory cell is "1" (the threshold voltage of the memory cell Vth&gt;read voltage 0V), the voltage of the bitline keeps precharge voltage. On the other hand, since the memory cell becomes "on" state if the programmed data in the memory cell is "0" (the threshold voltage of the memory cell Vth&lt;read voltage), the voltage of bitline BL falls only .DELTA.V from the precharge voltage. The data of the memory cell is read by detecting such a change of the voltage of the bitline BL by the sense amplifier.
In the data programming in the conventional NAND type, when "0" programming, in case that the memory cell which has more positive threshold voltage Vthcell than the memory cell to which "0" is programmed is exists on the bitline side, the "threshold voltage drop" occurs between the drain and the source of this memory cell. As a result, the voltage of the channel of the memory cell to which "0" is programmed becomes "Vcc-Vthcell". Thereafter, a floating channel is capacitive-coupled by the control gate and the voltage of the channel is set at the intermediate voltage. For example, when the capacity of the diffusion layer of the memory cell is as the capacity between the control gate and the channel, every time the control gate rises by 1V, the channel voltage goes up only 0.5V. In other words, the channel voltage of the memory cell can not be sufficiently enhanced. Therefore, the voltage difference between the control gate and the channel does not become sufficiently small, the unnecessary electrons are injected to the unselected memory cells which are unnecessary to program, and a mis-programming is occurred.
In the NAND type, when data is read from the memory cell selected for reading in the NAND cell, the other memory cells, i.e. all of unselected memory cells for reading are conducted. A memory cell which stores data "1" in the unselected memory cell for reading exists. In the reading of the present data, reading voltage Vread (e.g., Vcc) is given to the unselected control gate to conduct the unselected memory cell for reading. When the data of the unselected memory cell for reading is "0" at this time, there is possibility that so-called read disturb where electron is injected from the channel to the floating gate by the large electric field between the channel and the gate occurs. When read disturb occurs, data in the memory cell is destroyed. Especially, there is a problem that the read disturb occurs easier because threshold voltage Vth becomes higher than read voltage Vread, too, when the threshold voltage Vth of the memory cell of the programmed state becomes high with making a multi-value to cause read disturb more.
Moreover, there is a problem that, since a large read current is hardly obtained in a multi-level cell with high threshold voltage in the programmed state, the high-speed read operation is obstructed.
This is caused that a read current flowing through the memory cell depends on Vg-Vth and increases as that Vg-Vth is large, when Vgs is a voltage between the gate and the source of the memory cell and Vth is a threshold voltage of the memory cell at the time of the data reading.
The tendency that the threshold voltage Vth of the memory cell becomes high when making data a multi-level in this way, that large read current is hardly obtained and that the speeding-up of read operation is prevented is not only NAND type. It has a similar tendency in the NOR type in which memory cells connected in parallel between the source line and the bitline. In addition, it has a similar tendency in the AND type arid the DINOR type in which a plurality of memory cells are connected in parallel between the source line and the bitline as the unit cell.